`timescale 1ns / 1ps


module bnn_test(

    );
    reg clk;
    reg rst;
    wire reset_en, select_row, en_row, row_data,clk_3u,clko,clko2,f_fb_en,charge_en,add_bl_dis,switch_en_pump,comp_dis,comp_en,comp_adj;

 initial
 begin
 clk = 0;
 rst = 0;
 #1000 rst = 1;
//#54029000 rst = 0;
// #10000 rst = 1;
 end
always #5 clk =~ clk;

bnn uut (.clk(clk),.rst(rst),.reset_en(reset_en), .select_row(select_row), .en_row(en_row), .row_data1(row_data),.clk_3u(clk_3u),.clko(clko),.clko2(clko2),
.f_fb_en(f_fb_en),.charge_en(charge_en),.add_bl_dis(add_bl_dis),.switch_en_pump(switch_en_pump),.comp_dis(comp_dis),.comp_en(comp_en),.comp_adj(comp_adj));
endmodule